1. Field of the Invention
This invention generally relates to separation by implantation of oxygen (SIMOX) substrates for use in fabricating semiconductor wafers, and more particularly, to surface improvements of separation by implantation of oxygen substrates for use in fabricating semiconductor wafers.
2. Description of Related Art
Methods or processes used when fabricating semiconductor substrates or wafers for further use in the manufacture of semiconductor chips include silicon-on-insulator (SOI), and separation by implementation of oxygen (SIMOX). Known implantation techniques are used for forming buried layer devices known as silicon-on-insulator (SOI) devices using ion implanted oxygen. In these devices, a buried insulator layer is formed beneath a thin surface silicon film. Further wafer fabrication typically includes complementary metal oxide semiconductor (CMOS) processing.
The SIMOX method includes implanting oxygen in very heavy doses and annealing the wafer at a high temperature until a thin layer of SOI film is formed. Preferably, once the SOI film is made, putting transistors on the SOI film is done using similar processes as with a bulk CMOS wafer.
Specifically, SIMOX or separation by implementation of oxygen is a method of fabricating a silicon-on-insulator (SOI) material which can be used in the manufacturing of integrated circuits. SIMOX involves using high-energy ions to implant a large dose of oxygen ions beneath the surface of a bulk Si wafer. Upon high-temperature annealing, the implanted oxygen forms a continuous buried oxide layer, or BOX layer, which electrically isolates the Si at the surface, which is, the superficial layer.
Moreover, the annealing phase redistributes the oxygen ions such that the silicon/silicon dioxide boundaries become smoother and more abrupt, thus forming a sharp and well-defined BOX region. In addition to using annealing to clearly define the buried silicon dioxide layer, annealing can be used to repair damage to the top silicon layer. For example, a wafer can be heated to a temperature in the range from about 1300xc2x0 C. to about 1350xc2x0 C. for a duration of between about 2-12 hours.
A problem with the processing technique relates to the defect density. The defect density can be defined in terms of departure from perfect crystallinity in the by silicon layer that is separated from the bulk substrate by the buried oxide layer. In general, as the oxygen ions are implanted into the wafer to produce the buried silicon oxide layer, atomic silicon is replaced. Thereby, excess silicon atoms from the growing BOX layer can alter the crystal structure of the top silicon layer resulting in a variety of point and extended defects, such as threading dislocations and stacking faults, during the ion implantation and/or during the annealing process. These defects degrade the quality and reliability of devices, that is, transistors, that are subsequently formed in the upper silicon layer. Silicon wafers not processed by SIMOX processing include a surface morphology typically determined by a final polish, and do not experience the problems resulting from surface reformation when using SIMOX processing.
More specifically, rough silicon surfaces on substrates or wafers are undesirable in CMOS applications primarily due to poor gate oxide integrity. Complementary metal-oxide semiconductor (CMOS) based chips have impurities added to the wafer or silicon substrate in a doping process. This allows the chip to store an electrical charge which can be measured by ascertaining the capacitance. In order to control the electrical currents needed, the capacitance must be discharged and recharged which requires time, and causes the transistors on the chip to heat up. The transistor generates heat when the transistor, which is generally an electronic version of a switch, is on, and allowing current to flow therethrough.
Further, when fabricating a silicon wafer using CMOS processing, a rough silicon surface can adversely effect gate oxide integrity due to the electric field concentration at the sharp steps on the surface. As the gate oxides continue to scale to thinner films, the sharp steps on the surface of the silicon substrate become increasingly undesirable. A thin gate oxide, SiO2, typically in the range of 20 xc3x85-50 xc3x85 is used in all CMOS applications. Thus, the electrical integrity of this film is important for product yield and reliability.
Further, the substrate surface resulting from the silicon ingot is a factor in determining the surface morphology of the SIMOX processed silicon wafer. Once the SIMOX process is completed, the substrates surface morphology can vary in degrees of roughness and include surface abnormalities which render the silicon substrate or wafer undesirable for further processing. Further, undesirable SIMOX processed silicon wafers are disadvantageous because they represent a significant yield loss. Therefore, it is a significant problem in the industry when a processed wafer surface reconstructs after high temperature annealing to form a silicon wafer surface having undesirable surface roughness.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for improving surface morphology on a silicon substrate.
It is another object of the present invention to provide a method for repeatably providing high quality final surface morphology on a silicon substrate.
A further object of the invention is to provide a method for minimizing defect density in a silicon layer after SIMOX processing.
It is a further object of the present invention to provide a method for providing an improved surface morphology on a silicon substrate used in CMOS processing.
It is a further object of the present invention to provide a method for improving gate oxide integrity by providing repeatable high quality final surface morphology on a silicon substrate.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of improving surface morphology of a semiconductor substrate when using an SOI technique comprising providing a silicon ingot positioned on a support member, orientating the silicon ingot on the support member, and cutting the silicon ingot along about a (100) crystal plane of the silicon ingot to providing a silicon substrate having an initial surface. The method then further comprises processing the silicon substrate using SIMOX processing which includes implanting oxygen atoms in the silicon substrate to form a buried oxide layer and annealing the silicon substrate providing a final substrate surface. Preferably, cutting the silicon ingot includes a miscut angle between about 0-0.15 degrees from the (100) crystal plane. The silicon ingot is preferably cut using a wire saw.
After processing the silicon substrate, the method may include fabricating the final substrate surface using CMOS fabrication technique. Also, the method may further comprise measuring a surface morphology of the final substrate surface using an atomic force microscopy technique, and accepting the final substrate surface for CMOS processing when the final substrate surface measures between 2-20 angstroms RMS. After processing the silicon substrate, the final substrate surface may be polished using mirror polishing.
Orientating the silicon ingot may include aligning the ingot in relation to the support member and a cutting device to a predetermined position. After orientating the silicon ingot, the method may include verifying the position of the silicon ingot using x-ray diffraction.
In another aspect, the present invention provides a method of improving surface morphology of a semiconductor substrate when using an SOI technique comprising providing a silicon ingot positioned on a support member, orientating the silicon ingot in relation to the support member, and a cutting device, and cutting the silicon ingot along about a (100) crystal plane of the silicon ingot, preferably using a wire saw. This then provides a silicon substrate having an initial surface defining a miscut angle which is less than about 0.15 degrees from the (100) crystal plane. The method then comprises processing the silicon substrate using SIMOX processing, which includes implanting oxygen atoms in the silicon substrate to form a buried oxide layer and annealing the silicon substrate to provide a final substrate surface. Finally, the method includes accepting the final substrate surface for further processing when the final substrate surface measures between 2-20 xc3x85 RMS using an atomic force microscopy technique.
Preferably, after orientating the silicon ingot, the position of the silicon ingot is verified using x-ray diffraction. After accepting the final substrate surface, the method may include fabricating the final substrate surface using CMOS fabrication technique, or polishing the final substrate surface using mirror polishing. Orientating the silicon ingot preferably includes aligning the silicon ingot in relation to the support member and a cutting device to a predetermined position, and verifying the position of the silicon ingot using x-ray diffraction.
In a further aspect, the present invention provides a method of improving surface morphology of a semiconductor substrate when using an SOI technique comprising providing a silicon substrate including an initial surface having a miscut angle from a (100) crystal plane of less than about 0.15 degrees, and processing the silicon substrate using SIMOX processing. Such processing includes implanting oxygen atoms in the silicon substrate to form a buried oxide layer, and annealing the silicon substrate to provide a final substrate surface. Preferably, the final substrate surface measures between about 2-20 xc3x85 RMS using an atomic force microscopy technique. After processing the silicon substrate, the method may include fabricating the final substrate surface using a CMOS fabrication technique, polishing the final substrate surface using mirror polishing, or measuring a surface morphology of the final substrate surface using an atomic force microscopy technique and accepting the final substrate surface for CMOS processing when the final substrate surface measures between 2-20 angstroms RMS.